: These account for the propagation delays external to the chip. The guide details how to use set_input_delay and set_output_delay to model the environment at the chip’s boundary.
The 2021 documentation introduced enhanced support for advanced process nodes (7nm and below) where parasitic effects are dominant. synopsys timing constraints and optimization user guide 2021
: Leveraging clock gating and multi-threshold CMOS (MTCMOS) cells to reduce both dynamic and leakage power during the timing-closure process. 4. Advanced Features in the 2021 Release : These account for the propagation delays external
: Users are guided on choosing between Graph-Based Analysis (GBA) for speed and Path-Based Analysis (PBA) for higher accuracy during the final signoff stages. 3. Optimization Strategies synopsys timing constraints and optimization user guide 2021